module bit16_bit8(
    input               clk             ,
    input               rst_n           ,
    input               cam_vsync_16b   ,
    input               cam_href_16b    ,
    input       [15:0]  cam_data_16b    ,
    output              cam_vsync_8b    ,
    output              cam_hred_8b     ,
    output      [7:0]   cam_data_8b     
);

reg flag;
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        flag <= 1'd0;
    else if(cam_href_16b)
        flag <= ~flag;
    else
        flag <= 1'd0;
end

assign cam_data_8b  = flag ? cam_data_16b[7:0] : cam_data_16b[15:8];
assign cam_vsync_8b = cam_vsync_16b;
assign cam_hred_8b  = cam_href_16b;
endmodule